 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| MKE04P24M48SF0 ke04 sub-family data sheet supports the following: mke04z8vtg4(r), mke04z8vwj4(r), and mke04z8vfk4(r) key features ? operating characteristics C voltage range: 2.7 to 5.5 v C flash write voltage range: 2.7 to 5.5 v C temperature range (ambient): -40 to 105c ? performance C up to 48 mhz arm? cortex-m0+ core C single cycle 32-bit x 32-bit multiplier C single cycle i/o access port ? memories and memory interfaces C up to 8 kb flash C up to 1 kb ram ? clocks C oscillator (osc) - supports 32.768 khz crystal or 4 mhz to 24 mhz crystal or ceramic resonator; choice of low power or high gain oscillators C internal clock source (ics) - internal fll with internal or external reference, 37.5 khz pre- trimmed internal reference for 48 mhz system clock C internal 1 khz low-power oscillator (lpo) ? system peripherals C power management module (pmc) with three power modes: run, wait, stop C low-voltage detection (lvd) with reset or interrupt, selectable trip points C watchdog with independent clock source (wdog) C programmable cyclic redundancy check module (crc) C serial wire debug interface (swd) C aliased sram bitband region (bit-band) C bit manipulation engine (bme) ? security and integrity modules C 80-bit unique identification (id) number per chip ? human-machine interface C up to 22 general-purpose input/output (gpio) C two 8-bit keyboard interrupt modules (kbi) C external interrupt (irq) ? analog modules C one 12-channel 12-bit sar adc, operation in stop mode, optional hardware trigger (adc) C two analog comparators containing a 6-bit dac and programmable reference input (acmp) ? timers C one 6-channel flextimer/pwm (ftm) C one 2-channel flextimer/pwm (ftm) C one 2-channel periodic interrupt timer (pit) C one pulse width timer (pwt) C one real-time clock (rtc) ? communication interfaces C one spi module (spi) C one uart module (uart) C one i2c module (i2c) ? package options C 24-pin qfn C 20-pin soic C 16-pin tssop freescale semiconductor document number MKE04P24M48SF0 data sheet: technical data rev 3, 3/2014 freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. ? 2013-2014 freescale semiconductor, inc.
table of contents 1 ordering parts ........................................................................... 3 1.1 determining valid orderable parts...................................... 3 2 part identification ...................................................................... 3 2.1 description......................................................................... 3 2.2 format ............................................................................... 3 2.3 fields ................................................................................. 3 2.4 example ............................................................................ 4 3 parameter classification ............................................................ 4 4 ratings ...................................................................................... 4 4.1 thermal handling ratings ................................................... 4 4.2 moisture handling ratings .................................................. 5 4.3 esd handling ratings ......................................................... 5 4.4 voltage and current operating ratings ............................... 5 5 general ..................................................................................... 6 5.1 nonswitching electrical specifications ............................... 6 5.1.1 dc characteristics ................................................. 6 5.1.2 supply current characteristics ............................... 13 5.1.3 emc performance ................................................. 14 5.2 switching specifications..................................................... 15 5.2.1 control timing ........................................................ 15 5.2.2 ftm module timing ............................................... 16 5.3 thermal specifications ....................................................... 17 5.3.1 thermal characteristics ......................................... 17 6 peripheral operating requirements and behaviors .................... 19 6.1 core modules .................................................................... 19 6.1.1 swd electricals .................................................... 19 6.2 external oscillator (osc) and ics characteristics ............. 20 6.3 nvm specifications ............................................................ 22 6.4 analog ............................................................................... 23 6.4.1 adc characteristics............................................... 23 6.4.2 analog comparator (acmp) electricals ................. 25 6.5 communication interfaces ................................................. 26 6.5.1 spi switching specifications .................................. 26 7 dimensions ............................................................................... 29 7.1 obtaining package dimensions ......................................... 29 8 pinout ........................................................................................ 29 8.1 signal multiplexing and pin assignments .......................... 29 8.2 device pin assignment ...................................................... 31 9 revision history ......................................................................... 32 ke04 sub-family data sheet, rev3, 3/2014. 2 freescale semiconductor, inc. ordering parts 1.1 determining valid orderable parts valid orderable part numbers are provided on the web. to determine the orderable part numbers for this device, go to freescale.com and perform a part number search for the following device numbers: ke04z. part identification 2.1 description part numbers for the chip have fields that identify the specific part. you can use the values of these fields to determine the specific part you have received. 2.2 format part numbers for this device have the following format: q ke## a fff r t pp cc n 2.3 fields this table lists the possible values for each field in the part number (not all combinations are valid): field description values q qualification status ? m = fully qualified, general market flow ? p = prequalification ke## kinetis family ? ke04 a key attribute ? z = m0+ core fff program flash memory size ? 8 = 8 kb r silicon revision ? (blank) = main ? a = revision after main t temperature range (c) ? v = C40 to 105 pp package identifier ? tg = 16 tssop (4.5 mm x 5 mm) table continues on the next page... 1 2 ordering parts ke04 sub-family data sheet, rev3, 3/2014. freescale semiconductor, inc. 3 field description values ? wj = 20 soic (7 mm x 12 mm) ? fk = 24 qfn (4 mm x 4 mm) cc maximum cpu frequency (mhz) ? 4 = 48 mhz n packaging type ? r = tape and reel ? (blank) = trays 2.4 example this is an example part number: mke04z8vfk4 3 parameter classification the electrical parameters shown in this supplement are guaranteed by various methods. to give the customer a better understanding, the following classification is used and the parameters are tagged accordingly in the tables where appropriate: table 1. parameter classifications p those parameters are guaranteed during production testing on each individual device. c those parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations. t those parameters are achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. all values shown in the typical column are within this category. d those parameters are derived mainly from simulations. note the classification is shown in the column labeled c in the parameter tables where appropriate. ratings 4.1 thermal handling ratings symbol description min. max. unit notes t stg storage temperature C55 150 c 1 table continues on the next page... 4 parameter classification ke04 sub-family data sheet, rev3, 3/2014. 4 freescale semiconductor, inc. symbol description min. max. unit notes t sdr solder temperature, lead-free 260 c 2 1. determined according to jedec standard jesd22-a103, high temperature storage life . 2. determined according to ipc/jedec standard j-std-020, moisture/reflow sensitivity classification for nonhermetic solid state surface mount devices . 4.2 moisture handling ratings symbol description min. max. unit notes msl moisture sensitivity level 3 1 1. determined according to ipc/jedec standard j-std-020, moisture/reflow sensitivity classification for nonhermetic solid state surface mount devices . 4.3 esd handling ratings symbol description min. max. unit notes v hbm electrostatic discharge voltage, human body model C6000 +6000 v 1 v cdm electrostatic discharge voltage, charged-device model C500 +500 v 2 i lat latch-up current at ambient temperature of c C100 +100 ma 3 1. determined according to jedec standard jesd22-a114, electrostatic discharge (esd) sensitivity testing human body model (hbm) . 2. determined according to jedec standard jesd22-c101, field-induced charged-device model test method for electrostatic-discharge-withstand thresholds of microelectronic components . 3. determined according to jedec standard jesd78d, ic latch-up test . ? test was performed at 105 c case temperature (class ii). ? i/o pins pass 100 ma i-test with i dd current limit at 200 ma. ? i/o pins pass +30/-100 ma i-test with i dd current limit at 1000 ma. ? supply groups pass 1.5 vccmax. ? reset pin was only tested with negative i-test due to product conditioning requirement. 4.4 voltage and current operating ratings absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. stress beyond the limits specified in the following table may affect device reliability or cause permanent damage to the device. for functional operating conditions, refer to the remaining tables in this document. this device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance ratings ke04 sub-family data sheet, rev3, 3/2014. freescale semiconductor, inc. 5 circuit. reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for instance, either v ss or v dd ) or the programmable pullup resistor associated with the pin is enabled. table 2. voltage and current operating ratings symbol description min. max. unit v dd digital supply voltage C0.3 6.0 v i dd maximum current into v dd 120 ma v in input voltage except true open drain pins C0.3 v dd + 0.3 1 v input voltage of true open drain pins C0.3 6 v i d instantaneous maximum current single pin limit (applies to all port pins) C25 25 ma v dda analog supply voltage v dd C 0.3 v dd + 0.3 v 1. maximum rating of v dd also applies to v in . general nonswitching electrical specifications 5.1.1 dc characteristics this section includes information about power supply requirements and i/o pin characteristics. table 3. dc characteristics symbol c descriptions min typical 1 max unit operating voltage 2.7 5.5 v v oh p output high voltage all i/o pins, except pta2 and pta3, standard- drive strength 5 v, i load = C5 ma v dd C 0.8 v c 3 v, i load = C2.5 ma v dd C 0.8 v p high current drive pins, high-drive strength 2 5 v, i load = C20 ma v dd C 0.8 v c 3 v, i load = C10 ma v dd C 0.8 v i oht d output high current max total i oh for all ports 5 v C100 ma 3 v C60 v ol p output low voltage all i/o pins, standard- drive strength 5 v, i load = 5 ma 0.8 v c 3 v, i load = 2.5 ma 0.8 v p high current drive pins, high-drive strength 2 5 v, i load =20 ma 0.8 v c 3 v, i load = 10 ma 0.8 v table continues on the next page... 5 5.1 general ke04 sub-family data sheet, rev3, 3/2014. 6 freescale semiconductor, inc. table 3. dc characteristics (continued) symbol c descriptions min typical 1 max unit i olt d output low current max total i ol for all ports 5 v 100 ma 3 v 60 v ih p input high voltage all digital inputs 4.5v dd <5.5 v 0.65 v dd v 2.7v dd <4.5 v 0.70 v dd v il p input low voltage all digital inputs 4.5v dd <5.5 v 0.35 v dd v 2.7v dd <4.5 v 0.30 v dd v hys c input hysteresi s all digital inputs 0.06 v dd mv |i in | p input leakage current per pin (pins in high impedance input mode) v in = v dd or v ss 0.1 1 a |i intot | c total leakage combine d for all port pins pins in high impedance input mode v in = v dd or v ss 2 a r pu p pullup resistors all digital inputs, when enabled (all i/o pins other than pta2 and pta3) 30.0 50.0 k ? r pu 3 p pullup resistors pta2 and pta3 pins 30.0 60.0 k ? i ic d dc injection current 4 , 5 , 6 single pin limit v in < v ss , v in > v dd -2 2 ma total mcu limit, includes sum of all stressed pins -5 25 c in c input capacitance, all pins 7 pf v ram c ram retention voltage 2.0 v 1. typical values are measured at 25 c. characterized, not tested. 2. only ptb5, ptc1 and ptc5 support high current output. 3. the specified resistor value is the actual value internal to the device. the pullup value may appear higher when measured externally on the pin. 4. all functional non-supply pins, except for pta2 and pta3, are internally clamped to v ss and v dd . pta2 and pta3 are true open drain i/o pins that are internally clamped to v ss . 5. input must be current limited to the value specified. to determine the value of the required current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then use the larger value. 6. power supply must maintain regulation within operating v dd range during instantaneous and operating maximum current conditions. if the positive injection current (v in > v dd ) is higher than i dd , the injection current may flow out of v dd and could result in external power supply going out of regulation. ensure that external v dd load will shunt current higher than maximum injection current when the mcu is not consuming power, such as when no system clock is present, or clock rate is very low (which would reduce overall power consumption). nonswitching electrical specifications ke04 sub-family data sheet, rev3, 3/2014. freescale semiconductor, inc. 7 table 4. lvd and por specification symbol c description min typ max unit v por d por re-arm voltage 1 1.5 1.75 2.0 v v lvdh c falling low-voltage detect thresholdhigh range (lvdv = 1) 2 4.2 4.3 4.4 v v lvw1h c falling low- voltage warning threshold high range level 1 falling (lvwv = 00) 4.3 4.4 4.5 v v lvw2h c level 2 falling (lvwv = 01) 4.5 4.5 4.6 v v lvw3h c level 3 falling (lvwv = 10) 4.6 4.6 4.7 v v lvw4h c level 4 falling (lvwv = 11) 4.7 4.7 4.8 v v hysh c high range low-voltage detect/warning hysteresis 100 mv v lvdl c falling low-voltage detect thresholdlow range (lvdv = 0) 2.56 2.61 2.66 v v lvw1l c falling low- voltage warning threshold low range level 1 falling (lvwv = 00) 2.62 2.7 2.78 v v lvw2l c level 2 falling (lvwv = 01) 2.72 2.8 2.88 v v lvw3l c level 3 falling (lvwv = 10) 2.82 2.9 2.98 v v lvw4l c level 4 falling (lvwv = 11) 2.92 3.0 3.08 v v hysdl c low range low-voltage detect hysteresis 40 mv v hyswl c low range low-voltage warning hysteresis 80 mv v bg p buffered bandgap output 3 1.14 1.16 1.18 v 1. maximum is highest voltage that por is guaranteed. 2. rising thresholds are falling threshold + hysteresis. 3. voltage factory trimmed at v dd = 5.0 v, temp = 25 c nonswitching electrical specifications ke04 sub-family data sheet, rev3, 3/2014. 8 freescale semiconductor, inc. i oh (ma) v dd -v oh (v) figure 1. typical v dd -v oh vs. i oh (standard drive strength) (v dd = 5 v) i oh (ma) v dd -v oh (v) figure 2. typical v dd -v oh vs. i oh (standard drive strength) (v dd = 3 v) nonswitching electrical specifications ke04 sub-family data sheet, rev3, 3/2014. freescale semiconductor, inc. 9 i oh ( ma ) v dd - v oh (v) figure 3. typical v dd -v oh vs. i oh (high drive strength) (v dd = 5 v) i oh (ma) v dd -v oh (v) figure 4. typical v dd -v oh vs. i oh (high drive strength) (v dd = 3 v) nonswitching electrical specifications ke04 sub-family data sheet, rev3, 3/2014. 10 freescale semiconductor, inc. i ol ( ma ) v ol (v) figure 5. typical v ol vs. i ol (standard drive strength) (v dd = 5 v) i ol ( ma ) v ol (v) figure 6. typical v ol vs. i ol (standard drive strength) (v dd = 3 v) nonswitching electrical specifications ke04 sub-family data sheet, rev3, 3/2014. freescale semiconductor, inc. 11 i ol ( ma ) v ol (v) figure 7. typical v ol vs. i ol (high drive strength) (v dd = 5 v) i ol ( ma ) v ol (v) figure 8. typical v ol vs. i ol (high drive strength) (v dd = 3 v) nonswitching electrical specifications ke04 sub-family data sheet, rev3, 3/2014. 12 freescale semiconductor, inc. 5.1.2 supply current characteristics this section includes information about power supply current in various operating modes. table 5. supply current characteristics c parameter symbol core/bus freq v dd (v) typical 1 max 2 unit temp c run supply current fei mode, all modules clocks enabled; run from flash ri dd 48/24 mhz 5 10.1 ma -40 to 105 c c 24/24 mhz 7.1 c 12/12 mhz 4.4 c 1/1 mhz 2.1 c 48/24 mhz 3 9.9 c 24/24 mhz 6.9 c 12/12 mhz 4.2 1/1 mhz 1.9 c run supply current fei mode, all modules clocks disabled and gated; run from flash ri dd 48/24 mhz 5 7.4 ma -40 to 105 c c 24/24 mhz 5.2 c 12/12 mhz 3.5 c 1/1 mhz 2 c 48/24 mhz 3 7.2 c 24/24 mhz 5 c 12/12 mhz 3.3 c 1/1 mhz 1.8 c run supply current fbe mode, all modules clocks enabled; run from ram ri dd 48/24 mhz 5 13.2 ma -40 to 105 c p 24/24 mhz 9.1 9.5 c 12/12 mhz 5.1 c 1/1 mhz 1.8 c 48/24 mhz 3 13 p 24/24 mhz 9 9.4 c 12/12 mhz 5 c 1/1 mhz 1.7 c run supply current fbe mode, all modules clocks disabled and gated; run from ram ri dd 48/24 mhz 5 10.6 ma -40 to 105 c p 24/24 mhz 7.6 7.8 c 12/12 mhz 4.3 c 1/1 mhz 1.7 c 48/24 mhz 3 10.5 p 24/24 mhz 7.5 7.7 c 12/12 mhz 4.2 1/1 mhz 1.6 table continues on the next page... nonswitching electrical specifications ke04 sub-family data sheet, rev3, 3/2014. freescale semiconductor, inc. 13 table 5. supply current characteristics (continued) c parameter symbol core/bus freq v dd (v) typical 1 max 2 unit temp c wait mode current fei mode, all modules clocks enabled wi dd 48/24 mhz 5 7.2 ma -40 to 105 c p 24/24 mhz 6.3 6.5 c 12/12 mhz 3.6 c 1/1 mhz 1.9 c 48/24 mhz 3 7.1 p 24/24 mhz 6.2 6.4 c 12/12 mhz 3.5 c 1/1 mhz 1.8 p stop mode supply current no clocks active (except 1 khz lpo clock) 3 si dd 5 2 40 a -40 to 105 c p 3 1.9 39 -40 to 105 c c adc adder to stop adlpc = 1 adlsmp = 1 adco = 1 mode = 10b adiclk = 11b 5 86 a -40 to 105 c c 3 82 c acmp adder to stop 5 12 a -40 to 105 c c 3 12 c lvd adder to stop 4 5 130 a -40 to 105 c c 3 125 1. data in typical column was characterized at 5.0 v, 25 c or is typical recommended value. 2. the max current is observed at high temperature of 105 c. 3. rtc adder cause <1 a i dd increase typically, rtc clock source is 1 khz lpo clock. 4. lvd is periodically woken up from stop by 5% duty cycle. the period is equal to or less than 2 ms. 5.1.3 emc performance electromagnetic compatibility (emc) performance is highly dependent on the environment in which the mcu resides. board design and layout, circuit topology choices, location and characteristics of external components as well as mcu software operation play a significant role in emc performance. the system designer must consult the following freescale applications notes, available on freescale.com for advice and guidance specifically targeted at optimizing emc performance. ? an2321: designing for board level electromagnetic compatibility ? an1050: designing for electromagnetic compatibility (emc) with hcmos microcontrollers ? an1263: designing for electromagnetic compatibility with single-chip microcontrollers nonswitching electrical specifications ke04 sub-family data sheet, rev3, 3/2014. 14 freescale semiconductor, inc. ? an2764: improving the transient immunity performance of microcontroller-based applications ? an1259: system design and layout techniques for noise reduction in mcu- based systems 5.1.3.1 emc radiated emissions operating behaviors table 6. emc radiated emissions operating behaviors for 20-pin soic package symbol description frequency band (mhz) typ. unit notes v re1 radiated emissions voltage, band 1 0.15C50 11 db v 1 , 2 v re2 radiated emissions voltage, band 2 50C150 14 db v v re3 radiated emissions voltage, band 3 150C500 11 db v v re4 radiated emissions voltage, band 4 500C1000 5 db v v re_iec iec level 0.15C1000 m 2 , 3 1. determined according to iec standard 61967-1, integrated circuits - measurement of electromagnetic emissions, 150 khz to 1 ghz part 1: general conditions and definitions and iec standard 61967-2, integrated circuits - measurement of electromagnetic emissions, 150 khz to 1 ghz part 2: measurement of radiated emissionstem cell and wideband tem cell method . measurements were made while the microcontroller was running basic application code. the reported emission level is the value of the maximum measured emission, rounded up to the next whole number, from among the measured orientations in each frequency range. 2. v dd = 5.0 v, t a = 25 c, f osc = 8 mhz (crystal), f sys = 40 mhz, f bus = 20 mhz 3. specified according to annex d of iec standard 61967-2, measurement of radiated emissionstem cell and wideband tem cell method switching specifications 5.2.1 control timing table 7. control timing num c rating symbol min typical 1 max unit 1 d system and core clock f sys dc 48 mhz 2 p bus frequency (t cyc = 1/f bus ) f bus dc 24 mhz 3 p internal low power oscillator frequency f lpo 0.67 1.0 1.25 khz 4 d external reset pulse width 2 t extrst 1.5 t cyc ns 5 d reset low drive t rstdrv 34 t cyc ns 6 d irq pulse width asynchronous path 2 t ilih 100 ns d synchronous path 3 t ihil 1.5 t cyc ns table continues on the next page... 5.2 switching specifications ke04 sub-family data sheet, rev3, 3/2014. freescale semiconductor, inc. 15 table 7. control timing (continued) num c rating symbol min typical 1 max unit 7 d keyboard interrupt pulse width asynchronous path 2 t ilih 100 ns d synchronous path t ihil 1.5 t cyc ns 8 c port rise and fall time - normal drive strength (load = 50 pf) 4 t rise 10.2 ns c t fall 9.5 ns c port rise and fall time - high drive strength (load = 50 pf) 4 t rise 5.4 ns c t fall 4.6 ns 1. typical values are based on characterization data at v dd = 5.0 v, 25 c unless otherwise stated. 2. this is the shortest pulse that is guaranteed to be recognized as a reset pin request. 3. this is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. shorter pulses may or may not be recognized. in stop mode, the synchronizer is bypassed so shorter pulses can be recognized. 4. timing is shown with respect to 20% v dd and 80% v dd levels. temperature range -40 c to 105 c. ? ? ? ? ? ? ? ? t extrst reset_b pin figure 9. reset timing t ihil kbipx t ilih irq /kbipx figure 10. kbipx timing 5.2.2 ftm module timing synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that can be used as the optional external source to the timer counter. table 8. ftm input timing c function symbol min max unit d timer clock frequency f timer f bus f sys hz d external clock frequency f tclk 0 f timer /4 hz d external clock period t tclk 4 t cyc table continues on the next page... switching specifications ke04 sub-family data sheet, rev3, 3/2014. 16 freescale semiconductor, inc. table 8. ftm input timing (continued) c function symbol min max unit d external clock high time t clkh 1.5 t cyc d external clock low time t clkl 1.5 t cyc d input capture pulse width t icpw 1.5 t cyc ? ? ? ? ? ? ? ? t tclk t clkh t clkl tclk figure 11. timer external clock ? ? ? ? ? ? ? ? t icpw ftmchn t icpw ftmchn figure 12. timer input capture pulse thermal specifications 5.3.1 thermal characteristics this section provides information about operating temperature range, power dissipation, and package thermal resistance. power dissipation on i/o pins is usually small compared to the power dissipation in on-chip logic and voltage regulator circuits, and it is user- determined rather than being controlled by the mcu design. to take p i/o into account in power calculations, determine the difference between actual pin voltage and v ss or v dd and multiply by the pin current for each i/o pin. except in cases of unusually high pin current (heavy loads), the difference between pin voltage and v ss or v dd will be very small. 5.3 thermal specifications ke04 sub-family data sheet, rev3, 3/2014. freescale semiconductor, inc. 17 table 9. thermal attributes board type symbol description 24 qfn 20 soic 16 tssop unit notes single-layer (1s) r ja thermal resistance, junction to ambient (natural convection) 110 88 130 c/w 1 , 2 four-layer (2s2p) r ja thermal resistance, junction to ambient (natural convection) 42 61 87 c/w 1 , 3 single-layer (1s) r jma thermal resistance, junction to ambient (200 ft./min. air speed) 92 74 109 c/w 1 , 3 four-layer (2s2p) r jma thermal resistance, junction to ambient (200 ft./min. air speed) 36 55 80 c/w 1 , 3 r jb thermal resistance, junction to board 18 34 48 c/w 4 r jc thermal resistance, junction to case 3.7 37 33 c/w 5 jt thermal characterization parameter, junction to package top outside center (natural convection) 10 20 10 c/w 6 1. junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 2. per jedec jesd51-2 with the single layer board (jesd51-3) horizontal. 3. per jedec jesd51-6 with the board (jesd51-7) horizontal. 4. thermal resistance between the die and the printed circuit board per jedec jesd51-8. board temperature is measured on the top surface of the board near the package. 5. thermal resistance between the die and the solder pad on the bottom of the package. interface resistance is ignored. 6. thermal characterization parameter indicating the temperature difference between package top and the junction temperature per jedec jesd51-2. when greek letters are not available, the thermal characterization. the average chip-junction temperature (t j ) in c can be obtained from: t j = t a + (p d ja ) where: t a = ambient temperature, c ja = package thermal resistance, junction-to-ambient, c/w p d = p int + p i/o p int = i dd v dd , watts - chip internal power p i/o = power dissipation on input and output pins - user determined for most applications, p i/o << p int and can be neglected. an approximate relationship between p d and t j (if p i/o is neglected) is: p d = k (t j + 273 c) solving the equations above for k gives: thermal specifications ke04 sub-family data sheet, rev3, 3/2014. 18 freescale semiconductor, inc. k = p d (t a + 273 c) + ja (p d ) 2 where k is a constant pertaining to the particular part. k can be determined by measuring p d (at equilibrium) for an known t a . using this value of k, the values of p d and t j can be obtained by solving the above equations iteratively for any value of t a . 6 peripheral operating requirements and behaviors 6.1 core modules 6.1.1 swd electricals table 10. swd full voltage range electricals symbol description min. max. unit operating voltage 2.7 5.5 v j1 swd_clk frequency of operation ? serial wire debug 0 24 mhz j2 swd_clk cycle period 1/j1 ns j3 swd_clk clock pulse width ? serial wire debug 20 ns j4 swd_clk rise and fall times 3 ns j9 swd_dio input data setup time to swd_clk rise 10 ns j10 swd_dio input data hold time after swd_clk rise 3 ns j11 swd_clk high to swd_dio data valid 35 ns j12 swd_clk high to swd_dio high-z 5 ns j2 j3 j3 j4 j4 swd_clk (input) figure 13. serial wire clock input timing peripheral operating requirements and behaviors ke04 sub-family data sheet, rev3, 3/2014. freescale semiconductor, inc. 19 j11 j12 j11 j9 j10 input data valid output data valid output data valid swd_clk swd_dio swd_dio swd_dio swd_dio figure 14. serial wire data timing 6.2 external oscillator (osc) and ics characteristics table 11. osc and ics specifications (temperature range = -40 to 105 c ambient) num c characteristic symbol min typical 1 max unit 1 c crystal or resonator frequency low range (range = 0) f lo 31.25 32.768 39.0625 khz c high range (range = 1) f hi 4 24 mhz 2 d load capacitors c1, c2 see note 2 3 d feedback resistor low frequency, low-power mode 3 r f m ? low frequency, high-gain mode 10 m ? high frequency, low- power mode 1 m ? high frequency, high-gain mode 1 m ? 4 d series resistor - low frequency low-power mode 3 r s 0 k ? high-gain mode 200 k ? 5 d series resistor - high frequency low-power mode 3 r s 0 k ? table continues on the next page... peripheral operating requirements and behaviors ke04 sub-family data sheet, rev3, 3/2014. 20 freescale semiconductor, inc. table 11. osc and ics specifications (temperature range = -40 to 105 c ambient) (continued) num c characteristic symbol min typical 1 max unit d series resistor - high frequency, high-gain mode 4 mhz 0 k ? d 8 mhz 0 k ? d 16 mhz 0 k ? 6 c crystal start-up time low range = 32.768 khz crystal; high range = 20 mhz crystal 4 , 5 low range, low power t cstl 1000 ms c low range, high gain 800 ms c high range, low power t csth 3 ms c high range, high gain 1.5 ms 7 t internal reference start-up time t irst 20 50 s 8 p internal reference clock (irc) frequency trim range f int_t 31.25 39.0625 khz 9 p internal reference clock frequency, factory trimmed , t = 25 c, v dd = 5 v f int_ft 37.5 khz 10 p dco output frequency range fll reference = fint_t, flo, or fhi/rdiv f dco 40 50 mhz 11 p factory trimmed internal oscillator accuracy t = 25 c, v dd = 5 v f int_ft -0.5 0.5 % 12 c deviation of irc over temperature when trimmed at t = 25 c, v dd = 5 v over temperature range from -40 c to 105c f int_t -1.2 1 % over temperature range from 0 c to 105c f int_t -0.5 1 13 c frequency accuracy of dco output using factory trim value over temperature range from -40 c to 105c f dco_ft -1.7 1.5 % over temperature range from 0 c to 105c f dco_ft -1 1.5 14 c fll acquisition time 4 , 6 t acquire 2 ms 15 c long term jitter of dco output clock (averaged over 2 ms interval) 7 c jitter 0.02 0.2 %f dco 1. data in typical column was characterized at 5.0 v, 25 c or is typical recommended value. 2. see crystal or resonator manufacturer's recommendation. 3. load capacitors (c 1 ,c 2 ), feedback resistor (r f ) and series resistor (r s ) are incorporated internally when range = hgo = 0. 4. this parameter is characterized and not tested on each device. 5. proper pc board layout procedures must be followed to achieve specifications. 6. this specification applies to any time the fll reference source or reference divider is changed, trim value changed, or changing from fll disabled (fbelp, fbilp) to fll enabled (fei, fee, fbe, fbi). if a crystal/resonator is being used as the reference, this specification assumes it is already running. 7. jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f bus . measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. noise injected into the fll circuitry via v dd and v ss and variation in crystal oscillator frequency increase the c jitter percentage for a given interval. peripheral operating requirements and behaviors ke04 sub-family data sheet, rev3, 3/2014. freescale semiconductor, inc. 21 osc extal crystal or resonator r s c 2 r f c 1 xtal figure 15. typical crystal or resonator circuit 6.3 nvm specifications this section provides details about program/erase times and program/erase endurance for the flash memories. table 12. flash characteristics c characteristic symbol min 1 typical 2 max 3 unit 4 d supply voltage for program/erase C40 c to 105 c v prog/erase 2.7 5.5 v d supply voltage for read operation v read 2.7 5.5 v d nvm bus frequency f nvmbus 1 24 mhz d nvm operating frequency f nvmop 0.8 1 1.05 mhz d erase verify all blocks t vfyall 2605 t cyc d erase verify flash block t rd1blk 2579 t cyc d erase verify flash section t rd1sec 485 t cyc d read once t rdonce 464 t cyc d program flash (2 word) t pgm2 0.12 0.13 0.31 ms d program flash (4 word) t pgm4 0.21 0.21 0.49 ms d program once t pgmonce 0.20 0.21 0.21 ms d erase all blocks t ersall 95.42 100.18 100.30 ms d erase flash block t ersblk 95.42 100.18 100.30 ms d erase flash sector t erspg 19.10 20.05 20.09 ms d unsecure flash t unsecu 95.42 100.19 100.31 ms d verify backdoor access key t vfykey 482 t cyc d set user margin level t mloadu 415 t cyc c flash program/erase endurance t l to t h = -40 c to 105 c n flpe 10 k 100 k cycles table continues on the next page... peripheral operating requirements and behaviors ke04 sub-family data sheet, rev3, 3/2014. 22 freescale semiconductor, inc. table 12. flash characteristics (continued) c characteristic symbol min 1 typical 2 max 3 unit 4 c data retention at an average junction temperature of t javg = 85c after up to 10,000 program/erase cycles t d_ret 15 100 years 1. minimum times are based on maximum f nvmop and maximum f nvmbus 2. typical times are based on typical f nvmop and maximum f nvmbus 3. maximum times are based on typical f nvmop and typical f nvmbus plus aging 4. t cyc = 1 / f nvmbus program and erase operations do not require any special power sources other than the normal v dd supply. for more detailed information about program/erase operations, see the flash memory module section in the reference manual. 6.4 analog 6.4.1 adc characteristics table 13. 5 v 12-bit adc operating conditions characteri stic conditions symbol min typ 1 max unit comment supply voltage absolute v dda 2.7 5.5 v delta to v dd (v dd -v dda ) v dda -100 0 +100 mv input voltage v adin v refl v refh v input capacitance c adin 4.5 5.5 pf input resistance r adin 3 5 k ? analog source resistance 12-bit mode ? f adck > 4 mhz ? f adck < 4 mhz r as 2 5 k ? external to mcu 10-bit mode ? f adck > 4 mhz ? f adck < 4 mhz 5 10 8-bit mode (all valid f adck ) 10 adc conversion clock frequency high speed (adlpc=0) f adck 0.4 8.0 mhz low power (adlpc=1) 0.4 4.0 1. typical values assume v dda = 5.0 v, temp = 25c, f adck =1.0 mhz unless otherwise stated. typical values are for reference only and are not tested in production. peripheral operating requirements and behaviors ke04 sub-family data sheet, rev3, 3/2014. freescale semiconductor, inc. 23 adc sar engine simplified channel select circuit simplified input pin equivalent circuit pad leakage due to input protection z as r as c as v adin v as z adin r adin r adin r adin r adin input pin input pin input pin c adin figure 16. adc input impedance equivalency diagram table 14. 12-bit adc characteristics (v refh = v dda , v refl = v ssa ) characteristic conditions c symbol min typ 1 max unit supply current adlpc = 1 adlsmp = 1 adco = 1 t i dda 133 a supply current adlpc = 1 adlsmp = 0 adco = 1 t i dda 218 a supply current adlpc = 0 adlsmp = 1 adco = 1 t i dda 327 a supply current adlpc = 0 adlsmp = 0 adco = 1 t i dda 582 990 a supply current stop, reset, module off t i dda 0.011 1 a adc asynchronous clock source high speed (adlpc = 0) p f adack 2 3.3 5 mhz table continues on the next page... peripheral operating requirements and behaviors ke04 sub-family data sheet, rev3, 3/2014. 24 freescale semiconductor, inc. table 14. 12-bit adc characteristics (v refh = v dda , v refl = v ssa ) (continued) characteristic conditions c symbol min typ 1 max unit low power (adlpc = 1) 1.25 2 3.3 conversion time (including sample time) short sample (adlsmp = 0) t t adc 20 adck cycles long sample (adlsmp = 1) 40 sample time short sample (adlsmp = 0) t t ads 3.5 adck cycles long sample (adlsmp = 1) 23.5 total unadjusted error 2 12-bit mode t e tue 3.0 lsb 3 10-bit mode c 1.0 2.0 8-bit mode t 0.8 differential non- liniarity 12-bit mode t dnl 1.2 lsb 3 10-bit mode 4 c 0.3 1.0 8-bit mode 4 t 0.15 integral non-linearity 12-bit mode t inl 1.2 lsb 3 10-bit mode c 0.3 1.0 8-bit mode t 0.15 zero-scale error 5 12-bit mode t e zs 1.2 lsb 3 10-bit mode c 0.15 1.0 8-bit mode t 0.3 full-scale error 6 12-bit mode t e fs 1.8 lsb 3 10-bit mode c 0.7 1.0 8-bit mode t 0.5 quantization error 12 bit modes d e q 0.5 lsb 3 input leakage error 7 all modes d e il i in * r as mv temp sensor slope -40 cC25 c d m 3.266 mv/c 25 cC125 c 3.638 temp sensor voltage 25 c d v temp25 1.396 v 1. typical values assume v dda = 5.0 v, temp = 25 c, f adck =2.5 mhz under fbe mode and alternate clock source (altclk) is selected as adc clock. 2. includes quantization 3. 1 lsb = (v refh - v refl )/2 n 4. monotonicity and no-missing-codes guaranteed in 10-bit and 8-bit modes 5. v adin = v ssa 6. v adin = v dda 7. i in = leakage current (refer to dc characteristics) peripheral operating requirements and behaviors ke04 sub-family data sheet, rev3, 3/2014. freescale semiconductor, inc. 25 6.4.2 analog comparator (acmp) electricals table 15. comparator electrical specifications c characteristic symbol min typical max unit d supply voltage v dda 2.7 5.5 v t supply current (operation mode) i dda 10 20 a d analog input voltage v ain v ss - 0.3 v dda v p analog input offset voltage v aio 40 mv c analog comparator hysteresis (hyst=0) v h 15 20 mv c analog comparator hysteresis (hyst=1) v h 20 30 mv t supply current (off mode) i ddaoff 60 na c propagation delay t d 0.4 1 s 6.5 communication interfaces 6.5.1 spi switching specifications the serial peripheral interface (spi) provides a synchronous serial bus with master and slave operations. many of the transfer attributes are programmable. the following tables provide timing characteristics for classic spi timing modes. see the spi chapter of the chip's reference manual for information about the modified transfer formats used for communicating with slower peripheral devices. all timing is shown with respect to 20% v dd and 80% v dd , unless noted, and 25 pf load on all spi pins. all timing assumes slew rate control is disabled and high-drive strength is enabled for spi output pins. table 16. spi master mode timing nu m. symbol description min. max. unit comment 1 f op frequency of operation f bus /2048 f bus /2 hz f bus is the bus clock 2 t spsck spsck period 2 x t bus 2048 x t bus ns t bus = 1/f bus 3 t lead enable lead time 1/2 t spsck 4 t lag enable lag time 1/2 t spsck 5 t wspsck clock (spsck) high or low time t bus C 30 1024 x t bus ns 6 t su data setup time (inputs) 8 ns 7 t hi data hold time (inputs) 8 ns 8 t v data valid (after spsck edge) 25 ns 9 t ho data hold time (outputs) 20 ns 10 t ri rise time input t bus C 25 ns table continues on the next page... peripheral operating requirements and behaviors ke04 sub-family data sheet, rev3, 3/2014. 26 freescale semiconductor, inc. table 16. spi master mode timing (continued) nu m. symbol description min. max. unit comment t fi fall time input 11 t ro rise time output 25 ns t fo fall time output (output) 2 8 6 7 msb in 2 lsb in msb out 2 lsb out 9 5 5 3 (cpol=0) 4 11 11 10 10 spsck spsck (cpol=1) 2. lsbf = 0. for lsbf = 1, bit order is lsb, bit 1, ..., bit 6, msb. 1. if configured as an output. ss 1 (output) (output) mosi (output) miso (input) bit 6 . . . 1 bit 6 . . . 1 figure 17. spi master mode timing (cpha=0) < table 17. spi slave mode timing nu m. symbol description min. max. unit comment 1 f op frequency of operation 0 f bus /4 hz f bus is the bus clock as defined in control timing . 2 t spsck spsck period 4 x t bus ns t bus = 1/f bus 3 t lead enable lead time 1 t bus 4 t lag enable lag time 1 t bus 5 t wspsck clock (spsck) high or low time t bus - 30 ns 6 t su data setup time (inputs) 15 ns 7 t hi data hold time (inputs) 25 ns 8 t a slave access time t bus ns time to data active from high-impedance state 9 t dis slave miso disable time t bus ns hold time to high- impedance state 10 t v data valid (after spsck edge) 25 ns 11 t ho data hold time (outputs) 0 ns 12 t ri rise time input t bus - 25 ns t fi fall time input 13 t ro rise time output 25 ns t fo fall time output 2 10 6 7 msb in bit 6 . . . 1 slave msb slave lsb out 11 5 5 3 8 4 13 note: not defined 12 12 11 see note 13 9 see note (input) (cpol=0) spsck spsck (cpol=1) ss (input) (input) mosi (input) miso (output) lsb in bit 6 . . . 1 figure 19. spi slave mode timing (cpha = 0) peripheral operating requirements and behaviors ke04 sub-family data sheet, rev3, 3/2014. 28 freescale semiconductor, inc. 2 6 7 msb in bit 6 . . . 1 msb out slave lsb out 5 5 10 12 13 3 12 13 4 slave 8 9 see note (input) (cpol=0) spsck spsck (cpol=1) ss (input) (input) mosi (input) miso (output) note: not defined 11 lsb in bit 6 . . . 1 figure 20. spi slave mode timing (cpha=1) dimensions 7.1 obtaining package dimensions package dimensions are provided in package drawings. to find a package drawing, go to freescale.com and perform a keyword search for the drawings document number: if you want the drawing for this package then use this document number 16-pin tssop 98ash70247a 20-pin soic 98asb42343b 24-pin qfn 98asa00474d pinout 8.1 signal multiplexing and pin assignments the following table shows the signals available on each pin and the locations of these pins on the devices supported by this document. 7 8 dimensions ke04 sub-family data sheet, rev3, 3/2014. freescale semiconductor, inc. 29 note ? ptb5, ptc1, and ptc5 pins support high-current drive output, refer to the port_hdrve register in port control chapter for details. ? vdd and vrefh are internally connected. only one pin (vdd or vrefh) is available on chip. ? vss and vrefl are internally connected. only one pin (vss or vrefl) is available on chip. ? pta2 and pta3 are true open-drain pins when operated as output 24 qfn 20 soic 16 tsso p pin name default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 1 ptc5 disabled ptc5 kbi1_p1 ftm2_ch3 busout 2 ptc4 disabled ptc4 kbi1_p0 ftm2_ch2 pwt_in0 3 3 3 vdd vdd vdd 3 3 3 vrefh vdda/ vrefh vdda vrefh 4 4 4 vrefl vrefl vrefl 4 4 4 vss vss/ vssa vssa vss 5 5 5 ptb7 extal ptb7 i2c0_scl extal 6 6 6 ptb6 xtal ptb6 i2c0_sda xtal 7 7 7 ptb5 acmp1_out ptb5 kbi1_p7 ftm2_ch5 spi0_pcs acmp1_out 8 8 8 ptb4 nmi_b ptb4 kbi1_p6 ftm2_ch4 spi0_miso acmp1_in2 nmi_b 9 9 ptc3 adc0_se11 ptc3 kbi1_p5 ftm2_ch3 adc0_se11 10 10 ptc2 adc0_se10 ptc2 kbi1_p4 ftm2_ch2 adc0_se10 11 11 ptc1 adc0_se9 ptc1 kbi1_p3 ftm2_ch1 adc0_se9 12 12 ptc0 adc0_se8 ptc0 kbi1_p2 ftm2_ch0 adc0_se8 13 13 9 ptb3 adc0_se7 ptb3 kbi0_p7 spi0_mosi ftm0_ch1 adc0_se7 14 14 10 ptb2 adc0_se6 ptb2 kbi0_p6 spi0_sck ftm0_ch0 acmp0_in0 adc0_se6 15 15 11 ptb1 adc0_se5 ptb1 kbi0_p5 uart0_tx spi0_miso tclk2 adc0_se5 16 16 12 ptb0 adc0_se4 ptb0 kbi0_p4 uart0_rx spi0_pcs pwt_in1 adc0_se4 17 pta7 adc0_se3 pta7 ftm2_flt2 spi0_mosi acmp1_in1 adc0_se3 18 pta6 adc0_se2 pta6 ftm2_flt1 spi0_sck acmp1_in0 adc0_se2 19 17 13 pta3 disabled pta3 kbi0_p3 uart0_tx i2c0_scl 20 18 14 pta2 disabled pta2 kbi0_p2 uart0_rx i2c0_sda 21 19 15 pta1 adc0_se1 pta1 kbi0_p1 ftm0_ch1 acmp0_in1 adc0_se1 22 20 16 pta0 swd_clk pta0 kbi0_p0 ftm0_ch0 rtco acmp0_in2 adc0_se0 swd_clk 23 1 1 pta5 reset_b pta5 irq tclk1 reset_b 24 2 2 pta4 swd_dio pta4 acmp0_out swd_dio pinout ke04 sub-family data sheet, rev3, 3/2014. 30 freescale semiconductor, inc. 8.2 device pin assignment 24 23 22 pta4 pta5 pta0 pta2 pta3 21 20 19 pta1 ptb0 ptb1 16 15 pta6 pta7 18 17 ptb2 ptb3 14 13 ptc0 ptc1 ptc2 ptc3 12 11 10 9 ptb4 8 ptb5 7 ptb6 ptb7 vrefl vss vdd vrefh ptc4 ptc5 6 5 4 3 2 1 figure 21. 24-pin qfn package 20 18 17 11 12 13 14 15 16 dd /v refh ptb4 pta5 ptb5 ptc3 ptc2 1 2 3 4 5 6 7 8 9 10 19 v ss /v refl v ptb1 ptb0 pta3 pta2 pta1 pta0 pta4 ptc1 ptc0 ptb3 ptb2 ptb7 ptb6 figure 22. 20-pin soic package pinout ke04 sub-family data sheet, rev3, 3/2014. freescale semiconductor, inc. 31 1 2 3 4 5 6 7 8 dd /v refh ptb4 pta5 ptb5 v ss /v refl v pta4 ptb7 ptb6 ptb1 ptb0 pta3 pta2 pta1 pta0 ptb3 ptb2 16 15 14 13 12 11 10 9 figure 23. 16-pin tssop package 9 revision history the following table provides a revision history for this document. table 18. revision history rev. no. date substantial changes 3 3/2014 initial public release revision history ke04 sub-family data sheet, rev3, 3/2014. 32 freescale semiconductor, inc. how to reach us: home page: freescale.com web support: freescale.com/support information in this document is provided solely to enable system and software implementers to use freescale products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document. freescale reserves the right to make changes without further notice to any products herein. freescale makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does freescale assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. typical parameters that may be provided in freescale data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. all operating parameters, including typicals, must be validated for each customer application by customer's technical experts. freescale does not convey any license under its patent rights nor the rights of others. freescale sells products pursuant to standard terms and conditions of sale, which can be found at the following address: freescale.com/salestermsandconditions . freescale, the freescale logo, and kinetis are trademarks of freescale semiconductor, inc., reg. u.s. pat. & tm. off. all other product or service names are the property of their respective owners. arm and cortex-m0+ are the registered trademarks of arm limited. ?2013-2014 freescale semiconductor, inc. document number MKE04P24M48SF0 revision 3, 3/2014 |
Price & Availability of MKE04P24M48SF0
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |